Digital Logic is one of the most important subjects for computer science and electronics students. Whether you're preparing for competitive exams like GATE, IES, PSU, or technical interviews, practicing MCQs is the best way to strengthen your understanding.

In this post, we’ve compiled some of the most frequently asked Digital Logic MCQs with answers and brief explanations. These questions cover core topics such as logic gates, Boolean algebra, combinational circuits, flip-flops, and counters.

Each question will help you test your basics and improve your problem-solving speed for exams.


1. What input should be given to “S” when SR flip – flop is converted to JK flip – flop?

a) K.Q
b) K.Q
c) J.Q
d) J.Q^-

2. Which of the following digital logic circuits can be used to add more than 1 – bit simultaneously?
a) Full – adder
b) Ripple – carry adder
c) Half – adder
d) Serial adder

3. Which gates in Digital Circuits are required to convert a NOR-based SR latch to an SR flip-flop?
a) Two 2 input AND gates
b) Two 3 input AND gates
c) Two 2 input OR gates
d) Two 3 input OR gates

4. Which of the following options represent the synchronous control inputs in an S – R flip flop?
a) S
b) R
c) Clock
d) Both S and R

5. What must be used along with synchronous control inputs to trigger a change in the flip flop?
a) 0
b) 1
c) Clock
d) Previous output

6. When does a negative level triggered flip-flop in Digital Electronics changes its state?
a) When the clock is negative
b) When the clock is positive
c) When the inputs are all zero
d) When the inputs are all one

7. Which of the following majorly determines the number of emitters in a TTL digital circuit?
a) Fan – in
b) Fan – out
c) Propagation delay
d) Noise immunity

8. What will be the output from a D flip – flop if the clock is low and D = 0?
a) 0
b) 1
c) No change
d) Toggle between 0 and 1

9. What are the basic gates in MOS logic family?
a) NAND and NOR
b) AND and OR
c) NAND and OR
d) AND and NOR

10. What is the minimum distance required for single error detection according to Hamming’s analysis in Digital Electronics?
a) 1
b) 2
c) 3
d) 4

11. Which of these error-detecting codes enables to find double errors in Digital Electronic devices?
a) Parity method
b) Check sum method
c) Bit generation method
d) Odd-Even method

12. What will be the output from a D flip-flop if D = 1 and the clock is low?
a) No change
b) Toggle between 0 and 1
c) 0
d) 1

13. Which of the following gives the correct number of multiplexers required to build a 32 x 1 multiplexer?
a) Two 16 x 1 mux
b) Three 8 x 1 mux
c) Two 8 x 1 mux
d) Three 16 x 1 mux

14. What minimum distance is required for a single error correction according to Hamming’s analysis in Digital Electronics?
a) 1
b) 2
c) 3
d) 4

15. What must be the input given to “R” when SR flip – flop is converted to JK flip – flop?
a) K.Q
b) K.Q
c) J.Q
d) J.Q

16. How many AND gates are required to construct a 4 – bit parallel multiplier if four 4 – bit parallel binary adders are given?
a) Four 2 – input AND gates
b) Eight 2 – input AND gates
c) Sixteen 2 – input AND gates
d) Two 2 – input AND gates

17. The result “X + XY = X” follows which of these laws?
a) Consensus law
b) Distributive law
c) Duality law
d) Absorption law

18. Which of the following points is not correct regarding an Ex – NOR gate in Digital Electronics?
a) It is a one – bit comparator
b) It is a buffer
c) It is a one – bit inverter
d) It is a universal gate

19. Which gate is called the anti – coincidence and coincidence gate respectively?
a) XNOR and XOR
b) AND and OR
c) OR and AND
d) XOR and XNOR

20. Which of the following options are correct for a 4×1 multiplexer?
a) It has four 3 – input AND gates
b) It has four 2 – input AND gates
c) It has one 3 – input AND gate
d) It has one 3 – input AND gate

21. Any signed negative binary number is recognised by its ________
a) MSB
b) LSB
c) Byte
d) Nibble

22. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble

23. The representation of octal number (532.2)8 in decimal is ________
a) (346.25)10      (532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 = (346.25)10
b) (532.864)10
c) (340.67)10
d) (531.668)10

24. The decimal equivalent of the binary number (1011.011)2 is ________
a) (11.375)10 1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2-2 + 1 * 2-3 = (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10

25. The quantity of double word is ________
a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits

26. Octal to binary conversion: (24)8 =?
a) (111101)2
b) (010100)2
c) (111100)2
d) (101010)2

27. Convert binary to octal: (110110001010)2 =?
a) (5512)8
b) (6612)8
c) (4532)8
d) (6745)8

28. Code is a symbolic representation of __________ information.
a) Continuous
b) Discrete
c) Analog
d) Both continuous and discrete

29. In boolean algebra, the OR operation is performed by which properties?
a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned

30. The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A

31. According to boolean law: A + 1 = ?
a) 1
b) A
c) 0
d) A’

32. The involution of A is equal to _________
a) A
b) A’
c) 1
d) 0

33. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A

34. DeMorgan’s theorem states that _________
a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B

35. The output of an EX-NOR gate is 1. Which input combination is correct?
a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
d) A = 0, B’ = 1

36. In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR

37. The number of full and half adders are required to add 16-bit number is __________
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders

38. Which of the following gate is known as coincidence detector?
a) AND gate
b) OR gate
c) NOR gate
d) NAND gate

39. How many full adders are required to construct an m-bit parallel adder?
a) m/2
b) m
c) m-1
d) m+1

40. How many AND gates are required to realize Y = CD + EF + G?
a) 4
b) 5
c) 3
d) 2

41. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11

42. Which of the following are known as universal gates?
a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR

43. The gates required to build a half adder are __________
a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate

44. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16

45. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates

46. How many NAND circuits are contained in a 7400 NAND IC?
a) 1
b) 2
c) 4
d) 8

47. MSI means ___________
a) Merged Scale Integration
b) Main Scale Integration
c) Medium Scale Integration
d) Main Set Integration

48. Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1

49. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B

50. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B

51. The difference between half adder and full adder is __________
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned

52. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C

53. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1

54. Half subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits

55. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output

56. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4

57. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B

58. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B

59. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B

60. What does minuend and subtrahend denotes in a subtractor?
a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits

61. Full subtractor is used to perform subtraction of ___________
a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits

62. The full subtractor can be implemented using ___________
a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate

63. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
View Answer

64. The output of a full subtractor is same as ____________
a) Half adder
b) Full adder
c) Half subtractor
d) Decoder

65. 3 bits full adder contains ________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs

66. What is a multiplexer?
a) It is a type of decoder which decodes several inputs and gives one output
b) A multiplexer is a device which converts many signals into one
c) It takes one input and results into many output
d) It is a type of encoder which decodes several inputs and gives one output

67. How many select lines would be required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3

68. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
a) 3
b) 4
c) 2
d) 5

69. The enable input is also known as ___________
a) Select input
b) Decoded input
c) Strobe
d) Sink

70. A combinational circuit that selects one from many inputs are ____________
a) Encoder
b) Decoder
c) Demultiplexer
d) Multiplexer

71. The word demultiplex means ___________
a) One into many
b) Many into one
c) Distributor
d) One into many as well as Distributor

72. How many select lines are required for a 1-to-8 demultiplexer?
a) 2
b) 3        (2^3=8)
c) 4
d) 5

73. How many AND gates are required for a 1-to-8 multiplexer?
a) 2
b) 6
c) 8
d) 5

74. Which IC is used for the implementation of 1-to-16 DEMUX?
a) IC 74154
b) IC 74155
c) IC 74139
d) IC 74138

75. The basic building blocks of the arithmetic unit in a digital computers are ____________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator

76. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
b) Intermediate values
c) Both past output and present input
d) Present input values

77. All logic operations can be obtained by means of ____________
a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations

78. One way to make a four-bit adder to perform subtraction is by ___________
a) Inverting the output
b) Inverting the carry-in
c) Inverting the B inputs
d) Grounding the B inputs

79. What is one disadvantage of the ripple-carry adder?
a) The interconnections are more complex
b) More stages are required to a full adder
c) It is slow due to propagation time
d) All of the Mentioned

80. BCD adder can be constructed with 3 IC packages each of ____________
a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits

81. 3 bits full adder contains ____________
a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs

82. Decimal digit in BCD can be represented by ____________
a) 1 input line
b) 2 input lines
c) 3 input lines
d) 4 input lines